One use of a voltage regulator is to adjust a voltage of power applied to a load. In particular, a voltage regulator may be used to support Dynamic Voltage and Frequency Scaling (DVFS) in a master processor of a personal mobile device, such as a smart phone. In DVFS, a voltage regulator is used to adjust the voltage applied to circuitry in the master processor over an operable range to control the processing speed of master processor. Thus, it is desirable for a voltage regulator to change the applied voltage as quickly as possible to reduce latency in applying the desired voltage to circuitry.
One factor in the speed that a voltage regulator changes the applied voltage is the signaling needed by a control system to communicate with the voltage regulator to indicate that voltage change is desired. Several techniques have been used to reduce the amount of time needed due to the time needed for a voltage regulator to receive a voltage change command. In one technique, dedicated pins connected to control logic in a voltage regulator are used to provide signals that control the output voltage of the regulator. However, the use of dedicated pins causes physical area overhead in the packaging and the Printed Circuit Board (PCB) routing of the voltage regulator. In addition, the use of dedicated pins adds to the production costs of the voltage regulator.
A second technique uses a serial bus to communicate voltage change commands from the control system to the voltage regulator. The use of a bus does reduce the physical area overhead of a voltage regulator. However, the use of a serial bus may add transmission latency to the voltage change to account for the voltage regulator receiving the command. Typically, the latency added is along the order of the period of a clock multiplied by the length of a voltage change command.
For example, a Serial Peripheral Interface (SPI) bus using SPI protocol may be used to provide the voltage change commands from a control system to a voltage regulator. A typical SPI command includes one bit field to distinguish a read versus a write operation, an address field of one or more address bits, an optional transaction field of optional length bits, and a data field of one or more data bits. In addition, the SPI command may include pad bits before, after, and/or between any of the described fields. In most applications, an SPI command is at least 24 bits or 3 bytes long. Thus, the latency caused by the command is at least 24 multiplied by the period of the clock signal used to synchronize the SPI transfer.